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1. Asynchronous-FIFO Asynchronous-FIFO Public

   8 bit data width, 32 deep asynchronous FIFO

   Verilog

2. RTL_GDS_RV_SoC_Week_2 RTL_GDS_RV_SoC_Week_2 Public

   This repository contains the report of the Week 2 task for VSD RV SoC Tapeout Program

3. RTL_GDS_RV_SoC_Week_3 RTL_GDS_RV_SoC_Week_3 Public

   This repository contains the report of the Week 3 task for VSD RV SoC Tapeout Program

4. RTL_VEGA_SCA RTL_VEGA_SCA Public

   Verilog 1

5. Workspace_RTL_GDS_RV_SoC Workspace_RTL_GDS_RV_SoC Public

   This repository contains documentation of my weekly progress for RISC-V SoC Tapeout Program.

   Roff