diff --git a/regression/verilog/modules/instance_array1.desc b/regression/verilog/modules/instance_array1.desc
new file mode 100644
index 000000000..60b3153ff
--- /dev/null
+++ b/regression/verilog/modules/instance_array1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+instance_array1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This doesn't parse.
diff --git a/regression/verilog/modules/instance_array1.sv b/regression/verilog/modules/instance_array1.sv
new file mode 100644
index 000000000..3c0736a6e
--- /dev/null
+++ b/regression/verilog/modules/instance_array1.sv
@@ -0,0 +1,11 @@
+// 1800-2017 23.3.3.5
+
+module child(output o, input i[5]);
+   //...
+endmodule : child
+
+module parent(output o[8][4],
+              input i[8][4][5] );
+   child c[8][4](o,i);
+   //...
+endmodule : parent