Verilog: $signed(!0) is -1

This fixes the typing of $signed when given a Boolean argument.

Author: kroening

regression/verilog/system-functions/signed2.desc

@@ -0,0 +1,11 @@
+CORE
+signed2.sv
+--bound 0
+^\[main\.p0\] always \$signed\(1\) == 1: PROVED up to bound 0$
+^\[main\.p1\] always \$signed\(1'b1\) == -1: PROVED up to bound 0$
+^\[main\.p2\] always \$signed\(-1\) == -1: PROVED up to bound 0$
+^\[main\.p3\] always \$signed\(!0\) == -1: PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/system-functions/signed2.sv

@@ -0,0 +1,8 @@
+module main;
+
+  p0: assert final ($signed(1) == 1);
+  p1: assert final ($signed(1'b1) == -1);
+  p2: assert final ($signed(-1) == -1);
+  p3: assert final ($signed(!0) == -1);
+
+endmodule

src/verilog/verilog_typecheck_expr.cpp

@@ -784,7 +784,7 @@ exprt verilog_typecheck_exprt::convert_system_function(
     }
     else if(argument.type().id()==ID_bool)
     {
-      expr.type() = signedbv_typet{2};
+      expr.type() = signedbv_typet{1};
       return std::move(expr);
     }
     else