Merge pull request #874 from diffblue/include3

Verilog: KNOWNBUG test for include file name as a macro

Author: tautschnig

regression/verilog/preprocessor/include3.desc

@@ -0,0 +1,13 @@
+KNOWNBUG
+include2.v
+--preprocess
+// Enable multi-line checking
+activate-multi-line-match
+`line 1 "include3\.v" 0
+`line 1 "include_file2\.vh" 1
+
+`line 2 "include3\.v" 2
+^EXIT=0$
+^SIGNAL=0$
+--
+Giving the include file name as a macro doesn't work.

regression/verilog/preprocessor/include3.v

@@ -0,0 +1,3 @@
+`define SOME_INCLUDE "include_file2.vh"
+`include `SOME_INCLUDE
+